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HM5212165FLTD-75/A60/B60 HM5212805FLTD-75/A60/B60
Description
The HM5212165F L is a 128-Mbit S DRA M orga nized as 2097152-w ord x 16-bit x 4-ba nk. The HM5212805FL is a 128-Mbit SDRAM organized as 4194304-word x 8-bit x 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 54-pin plastic TSOP II.
Features
* * * * * * * *
3.3 V power supply Clock frequency: 133 MHz/100 MHz (max) LVTTL interface Single pulsed RAS 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 1/2/4/8/full page 2 variations of burst sequence Sequential (BL = 1/2/4/8/full page) Interleave (BL = 1/2/4/8) * Programmable CAS latency: 2/3 * Byte control by DQM : DQM (HM5212805FL) : DQMU/DQML (HM5212165FL) * Refresh cycles: 4096 refresh cycles/64 ms
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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128M LVTTL interface SDRAM 133 MHz/100 MHz 2-Mword x 16-bit x 4-bank/4-Mword x 8-bit x 4-bank PC/133, PC/100 SDRAM
E0180H10 (Ver. 1.0) Jul. 17, 2001
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This product became EOL in June, 2005.
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
* 2 variations of refresh Auto refresh Self refresh * Full page burst length capability Sequential burst Burst stop capability
Ordering Information
Type No.
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HM5212165FLTD-75* HM5212165FLTD-A60 HM5212165FLTD-B60*2 HM5212805FLTD-75*1 HM5212805FLTD-A60 HM5212805FLTD-B60*2
Notes: 1. 100 MHz operation at CAS latency = 2. 2. 66 MHz operation at CAS latency = 2.
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133 MHz 100 MHz 100 MHz 133 MHz 100 MHz 100 MHz
Frequency
CAS latency 3 2/3 3 3 2/3 3
Package 400-mil 54-pin plastic TSOP II (TTP-54DA)
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Data Sheet E0180H10
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Pin Arrangement (HM5212165F)
Pin Description
Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ15 CS RAS CAS WE Data-input/output Chip select Row address strobe command Column address strobe command Write enable A0 to A11 A0 to A8
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54-pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC DQML WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC
Bank select address A12/A13 (BS) VCC VSS
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Data Sheet E0180H10 3
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Pin name Function DQMU/DQML Input/output mask CLK Clock input CKE Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit VCCQ VSS Q NC Ground for DQ circuit No connection
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Pin Arrangement (HM5212805F)
Pin Description
Pin name A0 to A13 Function Address input Row address Column address DQ0 to DQ7 CS RAS CAS WE Data-input/output Chip select Row address strobe command Column address strobe command Write enable A0 to A11 A0 to A9
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54-pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ7 VSSQ NC DQ6 VCCQ NC DQ5 VSSQ NC DQ4 VCCQ NC VSS NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS
VCC DQ0 VCCQ NC DQ1 VSSQ NC DQ2 VCCQ NC DQ3 VSSQ NC VCC NC WE CAS RAS CS A13 A12 A10 A0 A1 A2 A3 VCC
Bank select address A12/A13 (BS) VCC VSS
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Data Sheet E0180H10
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Pin name DQM Function Input/output mask CLK Clock input CKE Clock enable Power for internal circuit Ground for internal circuit Power for DQ circuit VCCQ VSS Q NC Ground for DQ circuit No connection
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Block Diagram (HM5212165F)
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Memory array Bank0
Memory array Column decoder Bank1
Memory array Column decoder Bank2 4096 row x 512 column x 8 bit
Sense amplifier & I/O bus
Column decoder
Column decoder
Control logic & timing generator
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Column decoder
Column decoder
Column decoder
Column decoder
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Column address counter Row decoder 4096 row x 512 column x 8 bit Memory array Bank0 4096 row x 512 column x 8 bit Row decoder Column address counter
A0 to A13
Upper pellet
A0 to A8 Column address buffer
A0 to A13 Row address buffer Refresh counter
Row decoder
Row decoder
Row decoder
Memory array Bank3 4096 row x 512 column x 8 bit
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Input buffer DQ8 to DQ15 DQ0 to DQ7 Input buffer Bank1
4096 row x 512 column x 8 bit
Data Sheet E0180H10 5
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Output buffer Output buffer Memory array Memory array Bank2 4096 row x 512 column x 8 bit 4096 row x 512 column x 8 bit Row decoder Row decoder Column address buffer Row address buffer Refresh counter
CLK CKE CS RAS CAS WE DQMU /DQML
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Memory array Bank3 4096 row x 512 column x 8 bit Row decoder
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Block Diagram (HM5212805F)
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Memory array Bank0
Memory array Column decoder Bank1
Memory array Column decoder Bank2 4096 row x 1024 column x 4 bit
Sense amplifier & I/O bus
Column decoder
Column decoder
Control logic & timing generator
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Sense amplifier & I/O bus
Column decoder
Column decoder
Column decoder
Column decoder
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Column address counter Row decoder 4096 row x 1024 column x 4 bit Memory array Bank0 4096 row x 1024 column x 4 bit Row decoder Column address counter
A0 to A13
Upper pellet
A0 to A9 Column address buffer
A0 to A13 Row address buffer Refresh counter
Row decoder
Row decoder
Row decoder
Memory array Bank3 4096 row x 1024 column x 4 bit
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Input buffer DQ4 to DQ7 DQ0 to DQ3 Input buffer Bank1
4096 row x 1024 column x 4 bit
Data Sheet E0180H10
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Output buffer Output buffer Memory array Memory array Bank2 4096 row x 1024 column x 4 bit 4096 row x 1024 column x 4 bit Row decoder Row decoder Column address buffer Row address buffer Refresh counter
CLK CKE CS RAS CAS WE DQM
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Memory array Bank3 4096 row x 1024 column x 4 bit Row decoder
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK rising edge. CS (in pu t p in ): Whe n C S is Low, the command input cyc le bec omes valid. Whe n C S is High, all inputs ar e ignored. However, internal operations (bank active, burst operations, etc.) are held. RAS , CAS an d WE (in pu t p in s): Although these pin name s ar e the same as those of conve ntiona l DR AMs, they func tion in a diffe re nt wa y. The se pins def ine oper ation commands (r ea d, wr ite , etc .) depe nding on the combination of their voltage levels. For details, refer to the command operation section. A0 to A11 (in pu t p in s): R ow addr ess (A X0 to AX11) is dete rmined by A0 to A11 leve l at the bank ac tive command cycle CLK rising edge. Column address (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F) is dete rmined by A0 to A8 or A9 (A 8; HM5212165F , A9; HM5212805F ) leve l at the re ad or wr ite command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BS) is precharged. For details refer to the command operation section. A12/A13 (in p ut p in ): A12/A13 ar e bank sele ct signal (B S ). The memory ar ra y of the HM5212165F , the HM5212805F is divided into bank 0, bank 1, bank 2 and bank 3. HM5212165F conta in 4096-r ow x 512column x 16-bit. HM5212805F contain 4096-row x 1024-column x 8-bit. If A12 is Low and A13 is Low, bank 0 is sele cted. If A12 is High and A13 is Low, bank 1 is sele cted. If A12 is Low and A13 is High, bank 2 is selected. If A12 is High and A13 is High, bank 3 is selected. CKE (in pu t p in ): This pin dete rmines whe the r or not the next C LK is valid. If C KE is High, the next C LK rising edge is valid. If C KE is Low, the next C LK rising edge is invalid. This pin is used for powe r-dow n mode, clock suspend mode and self refresh mode. DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers.
R ea d oper ation: If DQM, DQMU /D QML is High, the output buff er bec omes High-Z. If the DQM, DQMU /D QML is Low, the output buff er bec omes Low- Z. (The latenc y of DQM, DQMU /D QML during reading is 2 clocks.) Wr ite oper ation: If DQM, DQMU /D QML is High, the pre vious data is held (the new data is not wr itten) . If DQM, DQMU /D QML is Low, the data is wr itten. (The latenc y of DQM, DQMU /D QML during wr iting is 0 clock.) DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5212165F, DQ0 to DQ7; HM5212805F). VCC and VCC Q (power supply pins): 3.3 V is applied. (V CC is for the internal circuit and VCCQ is for the output buffer.)
VSS an d VSS Q (p owe r sup p ly p in s): Gr ound is conne cte d. (V SS is for the internal cir cuit and VSS Q is for the output buffer.)
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Data Sheet E0180H10 7
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.
CKE n-1 n H H H x x x x x x x x x x x CS H L L L L L L L L L A0 RAS CAS WE A12/A13 A10 to A11 x H H H H H H L L L x H H L L L L H H H L x H L H H L L H L L H L x x x V V V V V V x x V x x x L H L H V L H x V x x x V V V V V x x x V
Command
Ignore command No operation
Burst stop in full page
Column address and read command READ Read with auto-precharge
Column address and write command WRIT Write with auto-precharge
Row address strobe and bank active ACTV Precharge select bank Precharge all bank Refresh Mode register set PRE
Note: H: VIH. L: VIL. x: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at the clock. However, the internal status is held. No op erat ion [N OP] : This command is not an exe cution command. Howe ver , the interna l oper ations continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (512; HM5212165F , 1024; HM5212805F )), and is ille gal other wise . Whe n data input/output is vompleted for a full page of data, it automatically returns to the start address and input/output is preformed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In addition, the start addr ess of burst re ad is dete rmined by the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9; HM5212805F) and the bank select address (BS). After the read operation, the output buffer becomes High-Z.
Re ad with au to-p re ch arge [R EAD A] : This command automatica lly per forms a pre cha rge oper ation af ter a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
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Symbol
DESL NOP
BST
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H READ A H H WRIT A H H H H PALL REF/SELF H MRS H
Data Sheet E0180H10
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Colu mn ad dr ess str obe an d wr it e com man d [WR IT ]: This command starts a wr ite oper ation. Whe n the burst wr ite mode is sele cted, the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9; HM5212805F ) and the bank sele ct addr ess (A 12/A 13) bec ome the burst wr ite start addr ess. Whe n the single wr ite mode is selected, data is only written to the location specified by the column address (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F) and the bank select address (A12/A13). Writ e with au to-p re ch arge [WR IT A] : This command automatica lly per forms a pre cha rge oper ation af ter a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page, this command is illegal. Row ad dr ess str obe an d b ank act ivate [A CTV ]: This command ac tiva tes the bank that is sele cted by A12/A13 (B S ) and dete rmines the row addr ess (A X0 to AX11) . Whe n A12 and A13 ar e Low, bank 0 is activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank 2 is activated. When A12 and A13 are High, bank 3 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register is spec ified by the addr ess pins (A 0 to A13) at the mode re giste r set cyc le. F or deta ils, re fe r to the mode re giste r conf iguration. Af te r powe r on, the conte nts of the mode re giste r ar e undef ined, exe cute the mode re giste r set command to set up the mode register.
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Data Sheet E0180H10 9
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
DQM Truth Table (HM5212165F)
Command
Upper byte (DQ8 to DQ15) write enable/output enable ENBU Lower byte (DQ0 to DQ7) write enable/output enable ENBL
Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU Lower byte (DQ0 to DQ7) write inhibit/output disable Note: H: VIH. L: VIL. x: VIH or VIL. Write: I DID is needed. Read: I DOD is needed. MASKL
DQM Truth Table (HM5212805F)
Command Write enable/output enable Write inhibit/output disable Note: H: VIH. L: VIL. x: VIH or VIL. Write: I DID is needed. Read: I DOD is needed.
The S DRA M ca n mask input/output data by mea ns of DQM, DQMU /D QML. DQMU masks the upper byte and DQML masks the lower byte (HM5212165F). Dur ing re ading, the output buff er is set to Low- Z by setting DQM, DQMU /D QML to Low, ena bling data output. On the other hand, whe n DQM, DQMU /D QML is set to High, the output buff er bec omes High-Z, disabling data output.
During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set to High, the pre vious data is held (the new data is not wr itten) . De sir ed data ca n be maske d during burst re ad or burst write by setting DQM, DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the SDRAM operating instructions.
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CKE Symbol n-1 H H H H n x x x x DQMU L x H x DQML x L x H
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Symbol ENB MASK Data Sheet E0180H10
CKE n-1 H n x x DQM L H
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
CKE Truth Table
CKE n-1 H L L H H H H L L L L n L L H H L L L H H H H CS x x x L L L H L H L H RAS x x x L L H x H x H x CAS x x x L L H x H x H x WE Address x x x H H H x H x H x x x x x x x x x x x x
Current state Active Any
Clock suspend Idle Idle Idle
Self refresh
Power down
Note: H: VIH. L: VIL. x: VIH or VIL.
Clock susp en d mod e en tr y: The S DRA M ente rs cloc k suspend mode fr om ac tive mode by setting C KE to Low. If command is input in the cloc k suspend mode entr y cyc le, the command is valid. The cloc k suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. RE AD susp en d an d RE AD with Au to-p re ch arge susp en d: The data being output is held (a nd continues to be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock susp en d mod e exit : The S DRA M exits fr om cloc k suspend mode by setting C KE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation.
Au to-r ef re sh com man d [R EF] : Whe n this command is input fr om the ID LE state, the S DRA M starts autore fre sh oper ation. (The auto- ref resh is the same as the C BR re fre sh of conve ntiona l DR AMs.) Dur ing the auto- ref resh oper ation, re fre sh addr ess and bank sele ct addr ess ar e gene ra te d inside the S DRA M. F or eve ry auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. B efor e exe cuting the auto- ref resh command, all the banks must be in the ID LE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge command is required after auto-refresh.
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Command Clock suspend Power down entry Power down exit
Clock suspend mode entry
Clock suspend mode exit Auto-refresh command (REF) Self-refresh entry (SELF)
Self refresh exit (SELFX)
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-refresh is performed internally and automatically, external refresh operations are unnecessary. Powe r d own mod e en tr y: Whe n this command is exe cute d during the ID LE state, the S DRA M ente rs powe r down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. S elf-r ef re sh exit : Whe n this command is exe cute d during self- re fre sh mode, the S DRA M ca n exit fr om selfrefresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state. Power down exit: When this command is executed at the power down mode, the SDRAM can exit from power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of the SDRAM. The following table assumes that CKE is high.
Current state Precharge CS H L L L L L L L L Idle H L L L L L L L L RAS x H H H H L L L L x H H H H L L L L CAS x H H L L H H L L x H H L L H H L L WE x Address x x x Command DESL Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL*4 ILLEGAL*4 ILLEGAL*4 NOP*6
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H L H L H L H L x H L H L H L H L x x x x x
Data Sheet E0180H10
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NOP BST BA, CA, A10 WRIT/WRIT A ACTV BA, RA BA, A10 PRE, PALL REF, SELF MODE MRS DESL NOP BST BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 ACTV PRE, PALL REF, SELF MODE MRS
BA, CA, A10 READ/READ A
BA, CA, A10 READ/READ A
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ILLEGAL ILLEGAL NOP NOP NOP ILLEGAL*5 ILLEGAL*5 Bank and row active NOP Refresh Mode register set
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Current state Row active CS H L L L L L L L L RAS x H H H H L L L L x CAS x H H L L WE x H L H L H L H L x Address x x x Command DESL NOP BST Operation NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop to full page Continue burst read to CAS latency and New read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and precharge
Read
Read with autoprecharge
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H H L L x H L L L L L L L L H L L L L L L L L H H H H L L L L x H H H H L L L L H H L L H H L L x H H L L H H L L
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x x x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
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H L H L H L H L x x H L H L H L H L x x x x
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A ACTV
Data Sheet E0180H10 13
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BA, RA BA, A10 PRE, PALL REF, SELF MODE MRS DESL NOP BST BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 ACTV PRE, PALL REF, SELF MODE MRS
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Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL ILLEGAL
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
Current state Write CS H L L L L L L L L Write with autoprecharge H L L L L L L L L Refresh (auto-refresh) H L L L L L L L L RAS x H H H H L L L L CAS x H H L L WE x H L H L H L H L x Address x x x Command DESL NOP BST Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and New read Term burst and New write Other bank active ILLEGAL on same bank*3 Term burst write and Precharge*2 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL*4 ILLEGAL*4 Other bank active ILLEGAL on same bank*3 ILLEGAL*4 ILLEGAL ILLEGAL
Notes: 1. H: VIH. L: VIL. x: VIH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If t RRD is not satisfied, this operation is illegal. 4. Illegal for same bank, except for another bank. 5. Illegal for all banks. 6. NOP for same bank, except for another bank.
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H H L L x x H H H H L L L L x H H H H L L L L H H L L H H L L x H H L L H H L L
BA, CA, A10 READ/READ A BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 x MODE x ACTV PRE, PALL REF, SELF MRS DESL NOP BST
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H L H L x x H L H L x H L H L H L H L x x x x x
Data Sheet E0180H10
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BA, CA, A10 WRIT/WRIT A ACTV BA, RA BA, A10 PRE, PALL REF, SELF MODE MRS DESL NOP BST BA, CA, A10 WRIT/WRIT A BA, RA BA, A10 ACTV PRE, PALL REF, SELF MODE MRS
BA, CA, A10 READ/READ A
BA, CA, A10 READ/READ A
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Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL*5 ILLEGAL*5 ILLEGAL*5 ILLEGAL*5 ILLEGAL ILLEGAL
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
From PRECHARGE state, command operation To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM enters the IDLE state after tRP has elapsed from the completion of precharge.
From IDLE state, command operation To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh). To [MRS]: The SDRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. T o [PR E] , [PA LL ]: The se commands set the S DRA M to pre cha rge mode. (H oweve r, an interva l of tRAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CAS latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.
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Data Sheet E0180H10 15
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HM5212165FLTD/HM5212805FLTD-75/A60/B60
From READ with AUTO-PRECHARGE state, command operation To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the SDRAM then enters precharge mode. T o [A CTV ]: This command make s other banks bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the SDRAM then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the SDRAM enters precharge mode. T o [A CTV ]: This command make s the other bank ac tive . (H oweve r, an interva l of tRRD is re quired. ) Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM automatically enters the IDLE state.
16
EO
L
Data Sheet E0180H10
Pr
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Simplified State Diagram
EO
Write WRITE SUSPEND CKE_ CKE CKE_ WRITEA SUSPEND CKE POWER APPLIED
SELF REFRESH SR ENTRY SR EXIT
MODE REGISTER SET
MRS IDLE
REFRESH
*1 AUTO REFRESH
CKE CKE_ IDLE POWER DOWN
Automatic transition after completion of command. Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state.
L
ACTIVE CLOCK SUSPEND
ACTIVE
CKE_ CKE
BST (on full page)
WRITE
WRITE WITH AP
WRITEA PRECHARGE
Pr
ROW ACTIVE WRITE READ WRITE WITH AP READ READ WITH AP WRITE READ READ WITH AP WRITE WITH AP PRECHARGE READA PRECHARGE PRECHARGE PRECHARGE
BST (on full page)
Read READ SUSPEND
CKE_ CKE
READ WITH AP
uc od
CKE_ CKE READA SUSPEND
POWER ON
t
Data Sheet E0180H10 17
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A13, A12, A11, A10, A9, A8: (OPCODE ): The S DRA M has two types of wr ite modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. B ur st re ad an d b ur st wr it e: B urst wr ite is per forme d for the spec ified burst length starting fr om the column address specified in the write cycle. B ur st re ad an d single wr it e: Da ta is only wr itten to the column addr ess spec ified during the wr ite cyc le, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length.
18
EO
A13 A12 A11 A10 A9 OPCODE 0 0 0 0 1 0 0 1 1 X A13 A12 A11 A10 0 X X X 0 X X X 0 X X X 0 X X X A9 0 0 1 1 A8 0 1 0 1
L
A8 A7 0 0 1 0 1 X R R 2 3 R Write mode R R
A6 A5 A4 CAS latency
Burst read and burst write
Burst read and single write
Data Sheet E0180H10
Pr
A6 A5 A4 A3 LMODE BT A3 Burst type 1 0 Sequential Interleave
A2
A1 BL
A0
A2 A1 A0 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 0 0
Burst length 1 2 4 1 2 4 8
uc od
BT=0 BT=1 8 R R R R R 1 0 1 R R 1 F.P. F.P. = Full Page (512: HM5212165) (1024: HM5212805) R is Reserved (inhibit) X: 0 or 1
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Burst Sequence
EO
Burst length = 2 A0 0 1 0, 1, 1, 0, Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 A0 0 1 0 1 Sequential 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0,
Starting Ad. Addressing(decimal) Sequential Interleave 0, 1, 1, 0,
Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6,
A0 Sequential
L
Data Sheet E0180H10 19
Pr
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Operation of the SDRAM
Read/Write Operations
B ank act ive: B efor e exe cuting a re ad or wr ite oper ation, the cor re sponding bank and the row addr ess must be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to the status of the A12/A13 pin, and the row addr ess (A X0 to AX11) is ac tiva ted by the A0 to A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (C AS latenc y-1) cyc le af ter re ad command set. HM5212165F , HM5212805F ca n per form a burst re ad operation. The burst length ca n be set to 1, 2, 4, 8 or full-pa ge (512; HM5212165F , 1024; HM5212805F ). The start addr ess for a burst re ad is spec ified by the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9; HM5212805F) and the bank select address (A12/A13) at the read command set cycle. In a read operation, data output starts af ter the number of cloc ks spec ified by the C AS latenc y. The C AS latenc y ca n be set to 2 or 3. Whe n the burst length is 1, 2, 4, 8, the Dout buff er automatica lly bec omes High-Z at the next cloc k af ter the successive burst-length data has been output. The CAS latency and burst length must be specified at the mode register.
CAS Latency
Command
20
EO
CLK t RCD
ACTV
L
READ Column
Pr
out 0 out 1 out 0 out 2 out 3 out 1 out 2
uc od
out 3 CL = CAS latency Burst Length = 4
Address
Row
Dout
CL = 2 CL = 3
t
Data Sheet E0180H10
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Burst Length
Command Address
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9, A8) of the mode register. 1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4, 8, and full-pa ge, like burst re ad oper ations. The wr ite start addr ess is spec ified by the column addr ess (AY0 to AY8; HM5212165F, AY0 to AY9; HM5212805F) and the bank select address (A12/A13) at the write command set cycle.
CLK
Command Address
EO
CLK
t RCD
ACTV
READ
Row
Column
BL = 1 BL = 2 BL = 4 BL = 8
out 0
out 0 out 1
Dout
out 0 out 1 out 2 out 3 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
out 0-1
L
WRIT
Column
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0
out 1
BL = full page
BL : Burst Length CAS Latency = 2
Pr
in 3 in 3 in 3 in 4 in 4 in 5 in 5 in 6 in 7 in 6 in 7 in 8
uc od
in 0-1
t RCD
ACTV
Row
BL = 1 BL = 2
in 0 in 0 in 1 in 1 in 1 in 1
in 2 in 2 in 2
Din
in 0
BL = 4
in 0
BL = 8
in 0
in 0
in 1
BL = full page
CAS Latency = 2, 3
t
Data Sheet E0180H10 21
HM5212165FLTD/HM5212805FLTD-75/A60/B60
2. S in gle wr it e: A single wr ite oper ation is ena bled by setting OP CO DE (A 9, A8) to (1, 0). In a single wr ite oper ation, data is only wr itten to the column addr ess (A Y0 to AY8; HM5212165F , AY0 to AY9; HM5212805F) and the bank select address (A12/A13) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
Auto Precharge
Re ad with au to-p re ch arge : In this oper ation, since pre cha rge is automatica lly per forme d af ter completing a re ad oper ation, a pre cha rge command nee d not be exe cute d af ter ea ch re ad oper ation. The command exe cute d for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by lAPR is required before execution of the next command.
CAS latency 3 2
Burst Read (Burst Length = 4)
CL=2 Command
CL=3 Command
22
EO
CLK Command Address Din
CLK ACTV DQ (input) ACTV DQ (input)
t RCD
WRIT
ACTV
Row
Column
Note: Internal auto-precharge starts at the timing indicated by " ". And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
L
READ A lRAS READ A lRAS
in 0
Precharge start cycle
2 cycle before the final data is output
1 cycle before the final data is output
Data Sheet E0180H10
Pr
out0 out1 out0
uc od
ACTV out2 out3 lAPR ACTV out1 out2 out3 lAPR
".
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Write with auto-precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command exe cute d for the same bank af ter the exe cution of this command must be the bank ac tive (A CTV ) command. In addition, an interva l of lAP W is re quired betwe en the fina l valid data input and input of next command. Burst Write (Burst Length = 4)
Single Write
EO
CLK Command
ACTV
WRIT A
ACTV
L
IRAS IRAS
DQ (input)
in0
in1
in2
in3 lAPW
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".
Pr
WRIT A
uc od
ACTV
CLK Command
ACTV
DQ (input)
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ". and an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge " ".
t
Data Sheet E0180H10 23
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-pa ge burst. The B ST command sets the output buff er to High-Z and stops the full-pa ge burst re ad. The timing from command input to the last data changes depending on the CAS latency setting. In addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
CAS latency 2 3 BST to valid data 1 2 BST to high impedance 2 3
CAS Latency = 2, Burst Length = full page
CAS Latency = 3, Burst Length = full page
24
EO
CLK Command DQ (output)
out out
CLK Command DQ (output) out out
L
BST
Data Sheet E0180H10
Pr
out out out l BSR = 1 clock
BST out out out
out
l BSH = 2 clocks
uc od
out out l BSR = 2 clocks l BSH = 3 clocks
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
B ur st stop com man d at b ur st wr it e: The burst stop command (B S T command) is used to stop data input during a full-pa ge burst wr ite . No data is wr itten in the same cloc k as the B ST command, and in subseque nt cloc ks. In addition, the B ST command is only valid during full-pa ge burst mode, and is ille gal with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge command. Burst Length = full page
Command DQ (input)
EO
CLK in
BST
PRE/PALL
L
in
t DPL
I BSW = 0 clock
Data Sheet E0180H10 25
Pr uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Command Intervals Read command to Read command interval: 1. Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cloc k. Eve n whe n the first command is a burst re ad that is not yet finished, the data re ad by the second command will be valid. READ to READ Command Interval (same ROW address in same bank)
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges on same bank, conse cutive re ad commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two re ad commands with a pre cha rge command and a bank-active command. 3. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cloc k, provide d that the other bank is in the bank- ac tive state. Eve n whe n the first command is a burst re ad that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank)
26
EO
CLK Command
Address
BS
ACTV
READ
L
READ Column A Column B
Row
Dout
Bank0 Active
out A0 out B0 out B1 out B2 out B3 Column =A Column =B Column =A Column =B Dout Read Read Dout
Pr
Bank0 Bank3 Dout Dout
CAS Latency = 3 Burst Length = 4 Bank 0
uc od
CAS Latency = 3 Burst Length = 4
CLK Command
Address
ACTV
Row 0
ACTV
Row 1
READ READ
Column A Column B
BS
Dout
Bank0 Active Bank3 Bank0 Bank3 Active Read Read
out A0 out B0 out B1 out B2 out B3
t
Data Sheet E0180H10
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Write command to Write command interval: 1. Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the pre ce ding wr ite command, the sec ond wr ite ca n be per forme d af ter an interva l of no less than 1 clock. In the case of burst writes, the second write command has priority. WRITE to WRITE Command Interval (same ROW address in same bank)
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands ca nnot be exe cute d; it is nec essa ry to sepa ra te the two wr ite commands with a pre cha rge command and a bank-active command. 3. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cloc k, provide d that the other bank is in the bank- ac tive state. In the ca se of burst wr ite , the sec ond wr ite command has priority. WRITE to WRITE Command Interval (different bank)
EO
CLK Command
Address
ACTV WRIT
Row
WRIT
L
Column A Column B
BS
Din
Bank0 Active
in A0
in B0
in B1
in B2
in B3
Column =A Column =B Write Write
Burst Write Mode Burst Length = 4 Bank 0
Pr
WRIT in B0 in B1 in B2 in B3
uc od
Burst Write Mode Burst Length = 4
CLK Command
Address
BS
ACTV ACTV WRIT
Row 0
Row 1
Column A Column B
Din
Bank0 Active
in A0
Bank3 Bank0 Bank3 Active Write Write
t
Data Sheet E0180H10 27
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Read command to Write command interval: 1. S ame b ank , same ROW ad dr ess: Whe n the wr ite command is exe cute d at the same R OW addr ess of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cloc k. Howe ver , DQM, DQMU /D QML must be set High so that the output buff er bec omes High-Z bef ore data input. READ to WRITE Command Interval (1)
READ to WRITE Command Interval (2)
2. S ame b ank , d if fer en t ROW ad dr ess: Whe n the R OW addr ess cha nges, conse cutive wr ite commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command.
3. Diff er en t b ank : Whe n the bank cha nges, the wr ite command ca n be per forme d af ter an interva l of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQM, DQMU/DQML must be set High so that the output buffer becomes High-Z before data input.
28
EO
CLK Command
DQM, CL=2 DQMU /DQML
READ WRIT
L
in B0 High-Z in B1 in B2 in B3
CL=3
Din
Dout
Burst Length = 4 Burst write
Pr
WRIT
CLK Command
READ
uc od
2 clock
DQM, DQMU/DQML
CL=2
High-Z
Dout
CL=3
High-Z
Din
t
Data Sheet E0180H10
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Write command to Read command interval: 1. S ame b ank , same ROW ad dr ess: Whe n the re ad command is exe cute d at the same R OW addr ess of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cloc k. Howe ver , in the ca se of a burst wr ite , data will continue to be wr itten until one cloc k bef ore the re ad command is executed. WRITE to READ Command Interval (1)
DQM, DQMU/DQML Din Dout
WRITE to READ Command Interval (2)
DQM, DQMU/DQML Din Dout Column = A Write Column = B Read in A0 in A1
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be exe cute d; it is nec essa ry to sepa ra te the two commands with a pre cha rge command and a bank- ac tive command.
3. Diff er en t b ank : Whe n the bank cha nges, the re ad command ca n be per forme d af ter an interva l of no less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one clock before the read command is executed (as in the case of the same bank and the same address).
EO
CLK Command WRIT in A0
CLK Command WRIT
READ
L
out B0 Column = A Write Column = B Read out B1 out B2 out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0 CAS Latency Column = B Dout
Data Sheet E0180H10 29
Pr
READ out B0 out B1 out B2 CAS Latency Column = B Dout
uc od
out B3 Burst Write Mode CAS Latency = 2 Burst Length = 4 Bank 0
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Read with auto precharge to Read command interval 1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is exe cute d. Eve n whe n the first re ad with auto- prec har ge is a burst re ad that is not yet finished, the data re ad by the sec ond command is valid. The interna l auto- prec har ge of one bank starts at the next cloc k of the sec ond command. Read with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command (the same bank) is illegal. Write with auto precharge to Write command interval
1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of one bank starts at the next clock of the second command . Write with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command (the same bank) is illegal.
30
EO
CLK Command BS Dout READ A bank0 Read A CLK Command BS Din in A0 bank0 Write A WRIT A
READ
Note: Internal auto-precharge starts at the timing indicated by "
Note: Internal auto-precharge starts at the timing indicated by "
L
WRIT in A1 in B0
out A0
out A1
out B0
out B1 CAS Latency = 3 Burst Length = 4
bank3 Read
".
Data Sheet E0180H10
Pr
in B1 in B2 bank3 Write ".
uc od
in B3 Burst Length = 4
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Read with auto precharge to Write command interval 1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond wr ite command (a nother bank) is exe cute d. Howe ver , DQM, DQMU /D QML must be set High so that the output buff er bec omes High-Z bef ore data input. The internal auto-precharge of one bank starts at the next clock of the second command. Read with Auto Precharge to Write Command Interval (Different bank)
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
EO
CLK Command BS DQM, DQMU/DQML CL = 2 CL = 3 Din Dout
READ A
WRIT
Note: Internal auto-precharge starts at the timing indicated by "
L
in B0 bank0 Read A bank3 Write
in B1
in B2
in B3
High-Z
Data Sheet E0180H10 31
Pr
Burst Length = 4
".
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Write with auto precharge to Read command interval 1. Diff er en t b ank : Whe n some banks ar e in the ac tive state, the sec ond re ad command (a nother bank) is exe cute d. Howe ver ,in ca se of a burst wr ite, data will continue to be wr itten until one cloc k bef ore the re ad command is executed. The internal auto-precharge of one bank starts at the next clock of the second command. Write with Auto Precharge to Read Command Interval (Different bank)
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It is necessary to separate the two commands with a bank active command.
32
EO
CLK Command BS WRIT A DQM, DQMU/DQML Din Dout in A0 bank0 Write A
READ
Note: Internal auto-precharge starts at the timing indicated by "
L
bank3 Read Data Sheet E0180H10
out B0
out B1
out B2
out B3 CAS Latency = 3 Burst Length = 4
Pr
".
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one clock. However, since the output buffer then becomes High-Z after the cloc ks def ined by lHZ P, ther e is a ca se of interr uption to burst re ad data output will be interr upte d, if the precharge command is input during burst read. To read all data by burst read, the clocks defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CAS Latency = 2, Burst Length = 4
CLK
Command
Dout
CAS Latency = 3, Burst Length = 4
CLK
Command
Dout
EO
READ CL=2 READ
L
out A0 CL=3
PRE/PALL
out A1
out A2
out A3
l EP = -1 cycle
Data Sheet E0180H10 33
Pr
PRE/PALL
uc od
out A1 out A2 out A3 l EP = -2 cycle
out A0
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
READ to PRECHARGE Command Interval (same bank): To stop output data CAS Latency = 2, Burst Length = 1, 2, 4, 8, full page burst
CLK
Command
Dout
CAS Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
CLK
Command
34
EO
READ
PRE/PALL
High-Z out A0
l HZP =2
READ
L
PRE/PALL
Pr
High-Z out A0 l HZP =3
Dout
Data Sheet E0180H10
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Writ e com man d to Pr ech arge com man d int er val (sam e b ank ): Whe n the pre cha rge command is exe cute d for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cloc k. Howe ver , if the burst wr ite oper ation is unfinished, the input data must be maske d by mea ns of DQM, DQMU/DQML for assurance of the clock defined by tDPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation)
DQM, DQMU/DQML Din
DQM, DQMU/DQML Din in A0
Burst Length = 4 (To write all data)
DQM, DQMU/DQML
EO
CLK Command WRIT
PRE/PALL
L
tDPL
Pr
PRE/PALL
CLK Command WRIT
in A1
uc od
PRE/PALL
tDPL
CLK Command WRIT
Din
in A0
in A1
in A2
in A3
tDPL
t
Data Sheet E0180H10 35
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Bank active command interval: 1. Same bank: The interval between the two bank-active commands must be no less than tRC. 2. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank Active to Bank Active for Same Bank
Bank Active to Bank Active for Different Bank
36
EO
CLK Command ACTV Address ROW BS Bank 0 Active
ACTV
L
t RC
ROW
Bank 0 Active
Pr
ACTV ROW:1 t RRD Bank 3 Active
CLK ACTV
Command
uc od t
Address
ROW:0
BS
Bank 0 Active
Data Sheet E0180H10
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Mod e re gister set to B ank -ac tive com man d int er val: The interva l betwe en setting the mode re giste r and executing a bank-active command must be no less than lRSA .
DQM Control
The DQM mask the DQ data . The DQMU and DQML mask the upper and lower bytes of the DQ data , respectively. The timing of DQMU/DQML is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQM, DQMU/DQML. By setting DQM, DQMU /D QML to Low, the output buff er bec omes Low- Z, ena bling data output. B y setting DQM, DQMU/DQML to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQM, DQMU/DQML during reading is 2 clocks. Writing: Input data can be masked by DQM, DQMU/DQML. By setting DQM, DQMU/DQML to Low, data ca n be wr itten. In addition, whe n DQM, DQMU /D QML is set to High, the cor re sponding data is not wr itten, and the previous data is held. The latency of DQM, DQMU/DQML during writing is 0 clock.
EO
CLK Command Address
MRS
ACTV
CODE
BS & ROW
L
I RSA Mode Register Set
Bank Active
Data Sheet E0180H10 37
Pr
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Reading
Writing
DQM, DQMU/DQML
DQ (input)
; ;;
Data Sheet E0180H10
38
EO
CLK DQM, DQMU/DQML DQ (output) CLK
High-Z out 0 out 1 out 3
lDOD = 2 Latency
L Pr
in 0 in 1 in 3 l DID = 0 Latency
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Refresh Au to-r ef re sh : All the banks must be pre cha rged bef ore exe cuting an auto- ref resh command. S inc e the autorefresh command updates the internal counter every time it is executed and determines the banks and the ROW addr esses to be re fre shed, exte rnal addr ess spec ifica tion is not re quired. The re fre sh cyc le is 4096 cyc les/64 ms. (4096 cyc les ar e re quired to re fre sh all the R OW addr esses. ) The output buff er bec omes High-Z af ter auto- ref resh start. In addition, since a pre cha rge has bee n complete d by an interna l oper ation af ter the autorefresh, an additional precharge operation by the precharge command is not required. S elf-r ef re sh : Af te r exe cuting a self- re fre sh command, the self- re fre sh oper ation continues while C KE is held Low. Dur ing self- re fre sh oper ation, all R OW addr esses ar e re fre shed by the interna l re fre sh time r. A selfre fre sh is ter mina te d by a self- re fre sh exit command. B efor e and af ter self- re fre sh mode, exe cute auto- ref resh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below. (1) Enter self-refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. (2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 s after exiting from self-refresh mode.
Others
Power-down mode: The SDRAM enters power-down mode when CKE goes Low in the IDLE state. In power down mode, powe r consumption is suppre sse d by dea ctivating the input initia l cir cuit. P ower down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM exits from the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is not performed. Clock susp en d mod e: B y driving C KE to Low during a bank- ac tive or re ad/wr ite oper ation, the S DRA M enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the SDRAM terminates clock suspend mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table". Power-up sequence: The SDRAM should be gone on the following sequence with power up.
The CLK, CKE, CS, DQM, DQMU/DQML and DQ pins keep low till power stabilizes. The CLK pin is stabilized within 100 s after power stabilizes before the following initialization sequence. The CKE and DQM, DQMU/DQML is driven to high between power stabilizes and the initialization sequence. This S DRA M has VCC cla mp diodes for C LK, C KE, C S, DQM, DQMU /D QML and DQ pins. If these pins go high before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 s or more has past after the above power-up sequence, all banks must be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands (REF). S et the mode re giste r set command (MR S) to initia liz e the mode re giste r. We re commend that by kee ping DQM, DQMU /D QML and C KE to High, the output buff er bec omes High-Z during Initializa tion seque nce , to avoid DQ bus contention on memory system formed with a number of device.
EO
L
Data Sheet E0180H10 39
Pr
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Power up sequence Initialization sequence 100 s 200 s
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to VSS .
DC Operating Conditions (Ta = 0 to +70C)
Parameter Supply voltage Symbol VCC, VCCQ VSS , VSS Q Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. VIH VIL
40
EO
VCC, VCCQ 0V CKE, DQM, DQMU/DQML CLK Low Low Low CS, DQ
Power stabilize
All voltage referred to VSS . The supply voltage with all VCC and VCCQ pins must be on the same level. The supply voltage with all VSS and VSS Q pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS .
L
Symbol VT Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 Unit V V mA W C C Note 1 1 Data Sheet E0180H10
Pr
VCC Iout PT 1.0 Topr 0 to +70 Tstg -55 to +125 Min 3.0 0 Max 3.6 0 2.0 -0.3 0.8
uc od
Unit Notes V 1, 2 V 3 VCC + 0.3 V 1, 4 V 1, 5
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
VIL/VIH Clamp
This SDRAM has VIL and VIH clamp for CLK, CKE, CS, DQM and DQ pins. Minimum VIL Clamp Current
VIL (V) -2
-1.8 -1.6 -1.4 -1.2 -1 -0.9 -0.8 -0.6 -0.4 -0.2 0
I (mA)
EO
0 -2 -5 -10 -15 -20 -25 -30 -35
I (mA) -32 -25 -19 -13 -8 -4 -2 -0.6 0
L
-1.5
Data Sheet E0180H10 41
Pr
0 0 0 -1 VIL (V)
-0.5
0
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Minimum VIH Clamp Current (referred to VCC)
VIH (V) I (mA) 10 8 5.5 3.5 1.5 0.3 0 0 0 0 0
VCC + 2
VCC + 1.8 VCC + 1.6 VCC + 1.4 VCC + 1.2 VCC + 1
VCC + 0.8 VCC + 0.6 VCC + 0.4 VCC + 0.2 VCC + 0
I (mA)
42
EO L
10 8 6 4 2 0 VCC + 0 VCC + 0.5
Data Sheet E0180H10
Pr uc od
VCC + 1.5 VCC + 2 VCC + 1 VIH (V)
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
IOL/IOH Characteristics
Output Low Current (I OL)
Vout (V) 0
0.4
0.65 0.85 1
1.4 1.5 1.65 1.8 1.95 3 3.45
IOL (mA)
EO
0 250 200 150 100 50 0 0 0.5 1
I OL
I OL Max (mA) 0 71 108 134 151 188 194 203 209 212 220 223
Min (mA)
27 41 51
58 70 72
L
75 77 77 80 81 1.5 2 Vout (V) 2.5 Data Sheet E0180H10
Pr uc od
min max 3 3.5
t
43
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Output High Current (I OH ) (Ta = 0 to +70C, VCC, VCCQ = 3.0 V to 3.45 V, VSS , VSS Q = 0 V)
I OH I OH Max (mA) -3 -28 -75 -130 -154 -197 -227 -248 -270 -285 -345 -503
Vout (V) 3.45 3.3 3
2.6 2.4 2
1.8
1.65 1.5 1.4 1 0
IOH (mA)
44
EO
0 0 0 0.5 1 -100 -200 -300 -400 -500 -600
Min (mA) -- --
-21 -34 -59 -67 -73 -78 -81 -89 -93
L
1.5 2 2.5 Vout (V) Data Sheet E0180H10
Pr
3
3.5
uc od
min max
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
DC Char acter istics (Ta = 0 to +70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) (HM5212165FL)
Parameter
Operating current (CAS latency = 2) (CAS latency = 3)
Standby current in power I CC2P down
Standby current in power I CC2PS down (input signal stable) Standby current in non I CC2N power down
Standby current in non I CC2NS power down (input signal stable) Active standby current in I CC3P power down Active standby current in I CC3PS power down (input signal stable) Active standby current in I CC3N non power down Active standby current in I CC3NS non power down (input signal stable) Burst operating current (CAS latency = 2) I CC4 (CAS latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current I CC4 I CC5 I CC6 I CC6 I LI
Output leakage current I LO Output high voltage Output low voltage VOH VOL
EO
Symbol I CC1 I CC1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -1 2.4 --
HM5212165FL -75 Min -A60 Max Min 120 120 3 2 -- -- -- -- -B60 Max Min 120 120 3 2 -- -- -- -- Max Unit 120 120 3 2 mA mA mA mA CKE = VIL, t CK = 12 ns 6 CKE = VIL, t CK = 7 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
L
15 10 -- -- 6 5 -- -- 35 24 -- -- 150 150 220 2 1 1 -- -- -- -- -- -1 -1.5 1.5 -- 0.4 2.4 --
15 10
-- --
15 10
mA mA
CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK =
4 9
Data Sheet E0180H10 45
Pr
6 5 -- -- 6 5 mA mA 35 24 -- -- 35 24 mA mA 120 120 220 2 1 1 -- -- -- -- -- 120 120 220 2 1 1 mA mA mA mA mA A -1 -1.5 1.5 -- 0.4 -1.5 1.5 2.4 -- -- A V 0.4 V
CKE = VIL, t CK = 12 ns 1, 2, 6 CKE = VIL, t CK = 2, 7
CKE, CS = VIH, t CK = 12 ns
1, 2, 4 2, 9
uc od
CKE = VIH, t CK = t CK = min, BL = 4 1, 2, 5 t RC = min 3 VIH VCC - 0.2 V VIL 0.2 V 8 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
DC Char acter istics (Ta = 0 to +70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) (HM5212805FL)
Parameter
Operating current (CAS latency = 2) (CAS latency = 3)
Standby current in power I CC2P down
Standby current in power I CC2PS down (input signal stable) Standby current in non I CC2N power down
Standby current in non I CC2NS power down (input signal stable) Active standby current in I CC3P power down Active standby current in I CC3PS power down (input signal stable) Active standby current in I CC3N non power down Active standby current in I CC3NS non power down (input signal stable) Burst operating current (CAS latency = 2) I CC4 (CAS latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current I CC4 I CC5 I CC6 I CC6 I LI
Output leakage current I LO Output high voltage Output low voltage VOH VOL
46
EO
Symbol I CC1 I CC1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -1 2.4 --
HM5212805FL -75 Min -A60 Max Min 120 120 3 2 -- -- -- -- -B60 Max Min 120 120 3 2 -- -- -- -- Max Unit 120 120 3 2 mA mA mA mA CKE = VIL, t CK = 12 ns 6 CKE = VIL, t CK = 7 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
L
15 10 -- -- 6 5 -- -- 35 24 -- -- 140 140 220 2 1 1 -- -- -- -- -- -1 -1.5 1.5 -- 0.4 2.4 --
15 10
-- --
15 10
mA mA
CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK =
4 9
Data Sheet E0180H10
Pr
6 5 -- -- 6 5 mA mA 35 24 -- -- 35 24 mA mA 110 110 220 2 1 1 -- -- -- -- -- 110 110 220 2 1 1 mA mA mA mA mA A -1 -1.5 1.5 -- 0.4 -1.5 1.5 2.4 -- -- A V 0.4 V
CKE = VIL, t CK = 12 ns 1, 2, 6 CKE = VIL, t CK = 2, 7
CKE, CS = VIH, t CK = 12 ns
1, 2, 4 2, 9
uc od
CKE = VIH, t CK = t CK = min, BL = 4 1, 2, 5 t RC = min 3 VIH VCC - 0.2 V VIL 0.2 V 8 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Notes: 1. I CC depends on output load condition when the device is selected. I CC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. After self refresh mode set, self refresh current. 9. Input signals are VIH or VIL fixed.
Capacitance (Ta = 25C, VCC, VCCQ = 3.3 V 0.3 V)
Parameter Input capacitance (CLK) Input capacitance (Input) Output capacitance (DQ) Notes: 1. 2. 3. 4.
EO
CI1 CI2 CO
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQM, DQMU/DQML = VIH to disable Dout. This parameter is sampled and not 100% tested.
L
Symbol 4
Min 2.5 2.5
Max 7 7 8
Unit pF pF pF
Notes 1, 2, 4 1, 2, 4 1, 2, 3, 4
Data Sheet E0180H10 47
Pr
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
AC Characteristics (Ta = 0 to +70C, VCC, VCCQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V)
HM5212165F/ HM5212805F -75 PC/100 Symbol Min Tclk Tclk Tch Tcl 10 7.5 2.5 2.5 -- -- 2.7 2 -- Max -- -- -- -- 6 5.4 -- -- 5.4 -A60 Min 10 10 3 3 -- -- 3 2 -- Max -- -- -- -- 6 6 -- -- 6 -B60 Min 15 10 3 3 -- -- 3 2 -- Max -- -- -- -- 8 6 -- -- 6 Unit Notes ns ns ns ns ns ns ns ns ns 1, 2 1, 2, 3 1, 4 1 1 1, 2 1
Parameter
System clock cycle time (CAS latency = 2) (CAS latency = 3)
CLK high pulse width CLK low pulse width
Access time from CLK (CAS latency = 2) (CAS latency = 3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance (CAS latency = 2, 3) Input setup time
CKE setup time for power down exit Input hold time Ref/Active to Ref/Active command period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period
Transition time (rise and fall) t T Refresh period t REF
48
EO
Symbol t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t CESP t RC t RAS t RCD t RP t DPL t RRD
L
Tac Tac Toh t AS , t CS, t DS, Tsi t CES Tpde t AH, t CH, t DH, Thi t CEH Trc Tras Trcd Trp Tdpl Trrd
Data Sheet E0180H10
Pr
1.5 -- -- -- 2 2 1 -- -- -- -- 1.5 0.8 67.5 -- 45 20 20 10 15 1 -- 70 120000 50 20 20 10 20 1 -- -- -- -- 5 -- -- -- -- 5 64 -- 64
2 2 1
-- -- -- --
ns ns ns ns
1, 5, 6 1 1, 5 1
uc od
70 120000 50 20 20 10 20 1 120000 ns ns ns ns ns 1 -- -- -- -- 5 1 1 1 1 ns -- 64 ms
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Notes: 1. 2. 3. 4. 5. 6. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CLK rising edge except power down exit command. t AS /tAH: Address t CS/tCH: CS, RAS, CAS, WE, DQM, DQMU/DQML t DS/tDH: Data-in t CES/tCEH : CKE
Test Conditions
* Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V
EO
input
0.4 V 2.0 V 0.8 V t
L
T
I/O CL
Data Sheet E0180H10 49
Pr
tT
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Relationship Between Frequency and Minimum Latency
HM5212165F/ HM5212805F -75 133 Symbol lRCD lRC lRAS lRP PC/100 Symbol 7.5 3 9 6 3 Tdpl 2 1 -A60/B60 100 10 2 7 5 2 1 2 1 3 7 Notes 1 = [lRAS+ lRP] 1 1 1 1 1 2 = [lDPL + lRP] = [lRC] 3
Parameter
Frequency (MHz) tCK (ns)
Active command to column command (same bank) Active command to active command (same bank)
Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) Active command to active command (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CAS latency = 2) (CAS latency = 3) Last data out to active command (auto precharge) (same bank)
Last data out to precharge (early precharge) (CAS latency = 2) (CAS latency = 3) Column command to column command Write command to data in latency DQM to data in DQM to data out CKE to CLK disable Register set to active command
50
EO
L
lDPL lRRD lSREX lAPW lSEC Tsrx Tdal lHZP lHZP lAPR Troh Troh lEP lEP lCCD lWCD lDID lDOD lCLE lRSA Tccd Tdwd Tdqm Tdqz Tcke Tmrd Data Sheet E0180H10
Pr
1 5 9 2 3 1 -1 -2 1 0 0 2 1 1
uc od
2 3 1 -1 -2 1 0 0 2 1 1
t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
HM5212165F/ HM5212805F Parameter -75 133 Symbol lCDD lPEC lBSR lBSR lBSH lBSH PC/100 Symbol 7.5 0 1 1 2 2 3 0 -A60/B60 100 10 0 1 1 2 2 3 0 Notes
Frequency (MHz) tCK (ns)
CS to command disable
Power down exit to command input Burst stop to output valid data hold (CAS latency = 2) (CAS latency = 3)
Burst stop to output high impedance (CAS latency = 2) (CAS latency = 3)
Burst stop to write data ignore
Notes: 1. lRCD to lRRD are recommended value. 2. Be valid [DESL] or [NOP] at next command of self refresh exit. 3. Except [DESL] and [NOP]
EO
L
lBSW Data Sheet E0180H10
Pr uc od t
51
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Timing Waveforms
Read Cycle
;; ;; ;;;
52
;; ;; ;;;; ; ;; ;;; ;;; ;;
t RCD t CS t CH t CS t CH t CS t CH t CS t CH
EO
t CK t CKH t CKL
CLK
t RC
VIH
CKE
t RAS
t RP
CS
t CS t CH
t CS t CH
L
t CS t CH t CS t CH t AS t AH t AS t AH t AS t AH t CS t AC Bank 0 Read t LZ
t CS t CH
t CS t CH
RAS
t CS t CH
t CS t CH
t CS t CH
CAS
t CS t CH
t CS t CH
t CS t CH
WE
Pr
t AS t AH t AS t AH t CH t AC t AC t AC t HZ t OH t OH t OH t OH Bank 0 Precharge
t AS t AH t AS t AH
t AS t AH t AS t AH
BS
A10
t AS t AH
t AS t AH
Address
DQM, DQMU/DQML
uc od
CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL
DQ (input)
DQ (output)
Bank 0 Active
t
Data Sheet E0180H10
;; ;; ;; ;;;;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Write Cycle
;;; ; ;
CS
t CS t CH t CS t CH t CS t CH t CS t CH
EO
t CK t CKH t CKL
CLK
t RC
VIH
CKE
t RCD
t RAS
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
RAS
t CS t CH
t CS t CH
t CS t CH
t CS t CH
L
t CS t CH t AS t AH t AS t AH t AS t AH t CS t DS t DH tDS Bank 0 Write
CAS
t CS t CH
t CS t CH
t CS t CH
WE
t AS t AH t AS t AH
t AS t AH
t AS t AH t AS t AH
BS
t AS t AH
Pr
t CH t DH t DS t DH t DS t DH t DPL Bank 0 Precharge
A10
t AS t AH
t AS t AH
Address
DQM, DQMU/DQML
DQ (input)
uc od
CAS latency = 2 Burst length = 4 Bank 0 access = VIH or VIL
DQ (output)
Bank 0 Active
t
53
Data Sheet E0180H10
;;;; ;;; ; ;;;;;;; ;;; ;; ;; ; ;;;;;; ; ;; ;;;; ;
Mode Register Set Cycle
0
;;;; ;;; ;; ; ;;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
DQM, DQMU/DQML DQ (output) DQ (input)
b High-Z l RP l RSA l RCD
Output mask Precharge If needed Mode Bank 3 register Active Set Bank 3 Read
Read Cycle/Write Cycle
0 1
2
3
4
5
6
7
8
9
10
11
12
13
CLK CS
CKE
VIH
RAS CAS WE BS
Address DQM, DQMU/DQML
R:a
C:a
R:b
C:b
C:b'
C:b"
DQ (output) DQ (input)
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
Bank 3 Read
High-Z
Bank 0 Active
Bank 0 Read
Bank 3 Active
Bank 3 Bank 0 Read Precharge
Bank 3 Read
CKE
VIH
CS
RAS CAS WE BS
Address DQM, DQMU/DQML DQ (output) DQ (input)
R:a
C:a
R:b
C:b
C:b'
C:b"
High-Z
a
a+1 a+2 a+3
Bank 3 Active
b
b+1 b+2 b+3 b'
Bank 0 Precharge
b'+1 b"
Bank 0 Active
Bank 0 Write
Bank 3 Write
Bank 3 Write
Bank 3 Write
Data Sheet E0180H10
54
;
b+3 b' b'+1 b'+2 b'+3
EO
1 2 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
CLK
CKE CS
VIH
RAS CAS
WE BS
Address
valid
code R: b
C: b
C: b'
L
l RCD = 3 CAS latency = 3 Burst length = 4 = VIH or VIL
Pr
14 15
16
17
18
19
20
Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL
uc od
b'+1 b" b"+1 b"+2 b"+3
Bank 3 Precharge
Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL
b"+1 b"+2 b"+3
t
Bank 3 Precharge
;;; ; ;; ; ;I ;;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Read/Single Write Cycle
0
;;; ;; ; ; ; ;
CLK CS CKE RAS CAS
VIH
EO
1 2 3 WE BS Address DQM, DQMU/DQML DQ (input) R:a C:a DQ (output)
Bank 0 Active Bank 0 Read
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:b
C:a' C:a a
L
a
Bank 3 Active
a+1 a+2 a+3
a
a+1 a+2 a+3
Bank 0 Precharge
Bank 0 Bank 0 Write Read
Bank 3 Precharge
CKE CS
VIH
RAS CAS
Pr
R:b C:a a b a a+1 a+3
Bank 3 Active Bank 0 Write
WE BS
Address DQM, DQMU/DQML DQ (input)
R:a
C:a
C:b C:c c
DQ (output)
Bank 0 Active
Bank 0 Read
Bank 0 Bank 0 Write Write
Bank 0 Precharge
Read/Single write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = V H or VIL
Data Sheet E0180H10 55
uc od
t
;; ; ; ;;; ;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Read/Burst Write Cycle
0 Address DQM, DQMU/DQML DQ (input) Address DQM, DQMU/DQML DQ (input)
; ;; ; ;
56
EO
1 2 3 CLK CS CKE RAS CAS BS WE R:a C:a DQ (output)
Bank 0 Active Bank 0 Read
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
R:b
C:a' a
L
a
Bank 3 Active
a+1 a+2 a+3
a+1 a+2 a+3
Clock suspend
Bank 0 Write
Bank 0 Precharge
Bank 3 Precharge
CKE CS
VIH
RAS CAS BS
Pr
R:b C:a a a a+1 a+3
Bank 3 Active Bank 0 Write
WE
R:a
C:a
a+1 a+2 a+3
DQ (output)
Bank 0 Active
Bank 0 Read
Bank 0 Precharge
Data Sheet E0180H10
uc od
Read/Burst write RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL
t
;;; ;; ;;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Full Page Read/Write Cycle
CLK CS
CKE RAS CAS
VIH
WE BS
Address DQM, DQMU/DQML DQ (output) DQ (input)
R:a
C:a
R:b
a
a+1
Bank 0 Active
Bank 0 Read
Bank 3 Active
CKE CS
VIH
RAS CAS BS
WE
Address DQM, DQMU/DQML DQ (output) DQ (input)
R:a
C:a
R:b
a
a+1
a+2
a+3
a+4
Bank 0 Active
Bank 0 Write
Bank 3 Active
; ;
Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL
a+2 a+3
EO
High-Z
Burst stop
Bank 3 Precharge
L
a+5
a+6
Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page = VIH or VIL
Data Sheet E0180H10 57
Pr
High-Z
Burst stop
Bank 3 Precharge
uc od
t
;;; ; ;;;; ;;; ;;; ; ;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Auto Refresh Cycle
0
;;;; ; ;;; ; ;;; ;; ;; ;;;;;;;; ; ;;;; ; ;; ;; ;;;; ;;; ; ; ; ;;; ;; ;; ;
Self Refresh Cycle
58
EO
1 2 3 4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CLK
CKE CS
VIH
RAS
CAS
WE BS
Address DQM, DQMU/DQML
A10=1
R:a
C:a
L
t RC
Auto Refresh
CKE Low Self refresh entry command
DQ (input)
DQ (output)
High-Z
a
a+1
t RP
tRC
Precharge If needed
Auto Refresh
Active Bank 0
Read Bank 0
Refresh cycle and Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL
Pr
l SREX
CLK
CKE CS
uc od
tRC tRC
Next clock enable Self refresh entry command Auto Next clock refresh enable
RAS CAS
WE BS
Address
A10=1
DQM, DQMU/DQML
DQ (input)
DQ (output)
High-Z
tRP
Precharge command If needed
Self refresh exit ignore command or No operation
Self refresh cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL
t
Data Sheet E0180H10
;;;; ;;; ;;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Clock Suspend Mode
t CES
t CEH
t CES
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
CLK CS
CKE RAS CAS BS
WE
Address DQM, DQMU/DQML DQ (output) DQ (input)
R:a
C:a
R:b
C:b
a
a+1 a+2
a+3
b
b+1 b+2 b+3
High-Z
Bank0 Active clock Active suspend start
Active clock Bank0 suspend end Read
Bank3 Active
Read suspend start
Read suspend end
Bank3 Read
Bank0 Precharge
Earliest Bank3 Precharge
CKE CS
RAS CAS BS
WE
Address DQM, DQMU/DQML DQ (output) DQ (input)
R:a
C:a R:b
C:b
High-Z
a
a+1 a+2
a+3 b
b+1 b+2 b+3
Bank0 Active
Active clock suspend start
Active clock Bank0 Bank3 supend end Write Active
Write suspend start
Write suspend end
Bank3 Bank0 Write Precharge
Earliest Bank3 Precharge
;
18 19 20
;;;;; ; ;;;; ; ; ;;; ;; ; ;;; ;;;;
Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL
EO
L
Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 = VIH or VIL
Data Sheet E0180H10
Pr
uc od
59
t
;; ;; ;; ; ; ;
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Power Down Mode Initialization Sequence
DQM, DQMU/DQML DQ
;; ;; ;;; ; ;;; ;; ;; ; ;; ;
0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55
;;; ; ;;; ;;; ;; ;; ;;; ; ; ;; ;; ; ;;
CKE CS
CKE Low
60
EO
CLK RAS CAS WE BS Address
A10=1
L
tRP
t RP
R: a
DQM, DQMU/DQML
DQ (input)
Pr
High-Z
t RC tRC
Auto Refresh
DQ (output)
Precharge command If needed
Power down entry
Power down mode exit Active Bank 0
Power down cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 = VIH or VIL
uc od
code Valid High-Z t RSA
Mode register Set Bank active If needed
CLK
CKE CS
VIH
RAS CAS
WE
Address
valid
VIH
All banks Precharge
Auto Refresh
t
Data Sheet E0180H10
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Package Dimensions
HM5212165FLTD/HM5212805FLTD (TTP-54DA)
Unit: mm
1
0.10 *0.30 + 0.05 - 0.28 0.05
0.80
27
0.13 M
10.16
*0.12 0.05 0.10 0.04
0.05 0.05
1.20 Max
0.10
0.50 0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-54DA -- -- 0.58 g
Data Sheet E0180H10 61
0.45
EO
22.22 22.72 Max 54 0.91 Max
28
L
11.76 0.20
0.80 0 - 5
Pr
uc od t
HM5212165FLTD/HM5212805FLTD-75/A60/B60
Cautions
1. Elpida Memory, Inc. neither warrants nor grants licenses of any rights of Elpida Memory, Inc.'s or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Elpida Memory, Inc. bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, contact Elpida Memory, Inc. before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Elpida Memory, Inc. particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. product does not cause bodily injury, fire or other consequential damage due to operation of the Elpida Memory, Inc. product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Elpida Memory, Inc.. 7. Contact Elpida Memory, Inc. for any questions regarding this document or Elpida Memory, Inc. semiconductor products.
62
EO
L
Data Sheet E0180H10
Pr
uc od t

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